In an image sensor, a signal output from a pixel (a signal read from a pixel) flows through a VSL (Vertical Signal Line), thereby changing the voltage of the VSL (hereinafter, referred to also as VSL voltage). The VSL voltage is acquired as a pixel value.
In order to increase the speed of the image sensor, it needs to shorten the setting time of the VSL voltage. However, the VSL has a parasitic capacitance, and the adverse effects of the parasitic capacitance block the shortening of the setting time of the VSL voltage.
Specifically, current flows in the VSL from the parasitic capacitance, thereby reducing current caused to flow by a current source as a load circuit, which constitutes an SF (Source Follower) with an amplification transistor constituting a pixel, by the amount corresponding to the current that flows in the VSL from the parasitic capacitance. The reduction in current caused to flow by the current source blocks the shortening of the setting time of the VSL voltage.
In view of the above, the applicant has proposed a technology that reduces adverse effects of a parasitic capacitance and shortens the setting time of the VSL voltage (furthermore, increase the speed of the image sensor (solid-state image sensor)) by connecting a replica circuit that increases the current caused to flow by the current source by the amount corresponding to the current that flows in the VSL from the parasitic capacitance to the VSL and causing current depending on the slew rate of the VSL to flow from the replica circuit to the VSL (see, for example, Patent Literature 1).